#define VIA_8363_KL133_REVISION_ID 0x81

#define VIA_8363_KL133_REVISION_ID 0x81

#define VIA_8363_KM133_REVISION_ID 0x84

#define VIA_8363_KM133_REVISION_ID 0x84

{

{

	u8 v;

	u8 v;

	u8 revision;

	u8 revision;

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);

/*

/*

 * For some reasons Intel decided that certain parts of their

 * For some reasons Intel decided that certain parts of their

 * issue another HALT within 80 ns of the initial HALT, the failure condition

 * issue another HALT within 80 ns of the initial HALT, the failure condition

 * is avoided.

 * is avoided.

 */

 */

{

{

	u32 val;

	u32 val;

	}

	}

}

}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

/* Max PCI Express root ports */

/* Max PCI Express root ports */

#define MAX_PCIEROOT	6

#define MAX_PCIEROOT	6

 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device

 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device

 * configuration space.

 * configuration space.

 */

 */

{

{

	u8 r;

	u8 r;

	/* clear 'F4 Video Configuration Trap' bit */

	/* clear 'F4 Video Configuration Trap' bit */

}

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,

			pci_early_fixup_cyrix_5530);

			pci_early_fixup_cyrix_5530);

	struct pci_dev * pci_dev = to_pci_dev(dev);

	struct pci_dev * pci_dev = to_pci_dev(dev);

	struct pci_driver * drv = pci_dev->driver;

	struct pci_driver * drv = pci_dev->driver;

	if (drv && drv->resume_early)

	if (drv && drv->resume_early)

		error = drv->resume_early(pci_dev);

		error = drv->resume_early(pci_dev);

	return error;

	return error;

/* Deal with broken BIOS'es that neglect to enable passive release,

/* Deal with broken BIOS'es that neglect to enable passive release,

   which can cause problems in combination with the 82441FX/PPro MTRRs */

   which can cause problems in combination with the 82441FX/PPro MTRRs */

{

{

	struct pci_dev *d = NULL;

	struct pci_dev *d = NULL;

	unsigned char dlc;

	unsigned char dlc;

	}

	}

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release );

/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround

/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround

    but VIA don't answer queries. If you happen to have good contacts at VIA

    but VIA don't answer queries. If you happen to have good contacts at VIA

 *	Updated based on further information from the site and also on

 *	Updated based on further information from the site and also on

 *	information provided by VIA 

 *	information provided by VIA 

 */

 */

{

{

	struct pci_dev *p;

	struct pci_dev *p;

	u8 rev;

	u8 rev;

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency );

/*

/*

 *	VIA Apollo VP3 needs ETBF on BT848/878

 *	VIA Apollo VP3 needs ETBF on BT848/878

 * TODO: When we have device-specific interrupt routers,

 * TODO: When we have device-specific interrupt routers,

 * this code will go away from quirks.

 * this code will go away from quirks.

 */

 */

{

{

	u8 tmp;

	u8 tmp;

	pci_write_config_byte (dev, 0x58, tmp);

	pci_write_config_byte (dev, 0x58, tmp);

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic );

/*

/*

 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.

 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.

 * Set this bit to get rid of cycle wastage.

 * Set this bit to get rid of cycle wastage.

 * Otherwise uncritical.

 * Otherwise uncritical.

 */

 */

{

{

	u8 misc_control2;

	u8 misc_control2;

#define BYPASS_APIC_DEASSERT 8

#define BYPASS_APIC_DEASSERT 8

	}

	}

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

/*

/*

 * The AMD io apic can hang the box when an apic irq is masked.

 * The AMD io apic can hang the box when an apic irq is masked.

#define AMD8131_revB0        0x11

#define AMD8131_revB0        0x11

#define AMD8131_MISC         0x40

#define AMD8131_MISC         0x40

#define AMD8131_NIOAMODE_BIT 0

#define AMD8131_NIOAMODE_BIT 0

{ 

{ 

        unsigned char revid, tmp;

        unsigned char revid, tmp;

        }

        }

} 

} 

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);

#endif /* CONFIG_X86_IO_APIC */

#endif /* CONFIG_X86_IO_APIC */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi );

/*

/*

 */

 */

	{ 0, },

	{ 0, },

};

};

{

{

	u8 irq, new_irq;

	u8 irq, new_irq;

		return;

		return;

	new_irq = dev->irq;

	new_irq = dev->irq;

	/* Don't quirk interrupts outside the legacy IRQ range */

	/* Don't quirk interrupts outside the legacy IRQ range */

	if (!new_irq || new_irq > 15)

	if (!new_irq || new_irq > 15)

		return;

		return;

	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);

	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);

	if (new_irq != irq) {

	if (new_irq != irq) {

			pci_name(dev), irq, new_irq);

			pci_name(dev), irq, new_irq);

		udelay(15);	/* unknown if delay really needed */

		udelay(15);	/* unknown if delay really needed */

		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);

		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);

	}

	}

}

}

/*

/*

 * VIA VT82C598 has its device ID settable and many BIOSes

 * VIA VT82C598 has its device ID settable and many BIOSes

 * do this even if the Linux CardBus driver is not loaded, because

 * do this even if the Linux CardBus driver is not loaded, because

 * the Linux i82365 driver does not (and should not) handle CardBus.

 * the Linux i82365 driver does not (and should not) handle CardBus.

 */

 */

{

{

	if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)

	if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)

		return;

		return;

	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);

	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);

DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);

/*

/*

 * Following the PCI ordering rules is optional on the AMD762. I'm not

 * Following the PCI ordering rules is optional on the AMD762. I'm not

 * To be fair to AMD, it follows the spec by default, its BIOS people

 * To be fair to AMD, it follows the spec by default, its BIOS people

 * who turn it off!

 * who turn it off!

 */

 */

{

{

	u32 pcic;

	u32 pcic;

	pci_read_config_dword(dev, 0x4C, &pcic);

	pci_read_config_dword(dev, 0x4C, &pcic);

	}

	}

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );

/*

/*

 *	DreamWorks provided workaround for Dunord I-3000 problem

 *	DreamWorks provided workaround for Dunord I-3000 problem

 * datasheets found at http://www.national.com/ds/GX for info on what

 * datasheets found at http://www.national.com/ds/GX for info on what

 * these bits do.  <christer@weinigel.se>

 * these bits do.  <christer@weinigel.se>

 */

 */

{

{

	u8 reg;

	u8 reg;

	pci_read_config_byte(dev, 0x41, &reg);

	pci_read_config_byte(dev, 0x41, &reg);

	}

	}

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );

/*

/*

 *	Ensure C0 rev restreaming is off. This is normally done by

 *	Ensure C0 rev restreaming is off. This is normally done by

 *	the BIOS but in the odd case it is not the results are corruption

 *	the BIOS but in the odd case it is not the results are corruption

 *	hence the presence of a Linux check

 *	hence the presence of a Linux check

 */

 */

{

{

	u16 config;

	u16 config;

	u8 rev;

	u8 rev;

	}

	}

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb );

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb );

/*

/*

 * runs everywhere at present we suppress the printk output in most

 * runs everywhere at present we suppress the printk output in most

 * irrelevant cases.

 * irrelevant cases.

 */

 */

{

{

	unsigned char val;

	unsigned char val;

	}

	}

}

}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);

/*

/*

 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge

 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge

 * is not activated. The myth is that Asus said that they do not want the

 * is not activated. The myth is that Asus said that they do not want the

 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 

 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 

 * becomes necessary to do this tweak in two steps -- I've chosen the Host

 * becomes necessary to do this tweak in two steps -- I've chosen the Host

 * bridge as trigger.

 * bridge as trigger.

 */

 */

static int __initdata asus_hides_smbus;

static int __initdata asus_hides_smbus;

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );

{

{

	u16 val;

	u16 val;

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc );

{

{

	u32 val, rcba;

	u32 val, rcba;

	void __iomem *base;

	void __iomem *base;

	printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");

	printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");

}

}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6 );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6 );

/*

/*

 * SiS 96x south bridge: BIOS typically hides SMBus device...

 * SiS 96x south bridge: BIOS typically hides SMBus device...

 */

 */

{

{

	u8 val = 0;

	u8 val = 0;

	printk(KERN_INFO "Enabling SiS 96x SMBus.\n");

	printk(KERN_INFO "Enabling SiS 96x SMBus.\n");

#define SIS_DETECT_REGISTER 0x40

#define SIS_DETECT_REGISTER 0x40

{

{

	u8 reg;

	u8 reg;

	u16 devid;

	u16 devid;

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_735,		quirk_sis_96x_compatible );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_735,		quirk_sis_96x_compatible );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503 );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503 );

/*

/*

 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller

 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller

 * and MC97 modem controller are disabled when a second PCI soundcard is

 * and MC97 modem controller are disabled when a second PCI soundcard is

 * present. This patch, tweaking the VT8237 ISA bridge, enables them.

 * present. This patch, tweaking the VT8237 ISA bridge, enables them.

 * -- bjd

 * -- bjd

 */

 */

{

{

	u8 val;

	u8 val;

	int asus_hides_ac97 = 0;

	int asus_hides_ac97 = 0;

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus );

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus );

#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)

#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)

/*

/*

 *	the PCI scanning.

 *	the PCI scanning.

 */

 */

{

{

	u32 conf;

	u32 conf;

	u8 hdr;

	u8 hdr;

}

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);

#endif

#endif

extern struct pci_fixup __end_pci_fixups_final[];

extern struct pci_fixup __end_pci_fixups_final[];

extern struct pci_fixup __start_pci_fixups_enable[];

extern struct pci_fixup __start_pci_fixups_enable[];

extern struct pci_fixup __end_pci_fixups_enable[];

extern struct pci_fixup __end_pci_fixups_enable[];

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)

		end = __end_pci_fixups_enable;

		end = __end_pci_fixups_enable;

		break;

		break;

	default:

	default:

		/* stupid compiler warning, you would think with an enum... */

		/* stupid compiler warning, you would think with an enum... */

		return;

		return;

 * Force it to be linked by setting the corresponding control bit in the

 * Force it to be linked by setting the corresponding control bit in the

 * config space.

 * config space.

 */

 */

{

{

	uint8_t b;

	uint8_t b;

	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {

	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {

}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,

			quirk_nvidia_ck804_pcie_aer_ext_cap);

			quirk_nvidia_ck804_pcie_aer_ext_cap);

#ifdef CONFIG_PCI_MSI

#ifdef CONFIG_PCI_MSI

/* To disable MSI globally */

/* To disable MSI globally */

const struct pci_device_id *pci_find_present(const struct pci_device_id *ids)

const struct pci_device_id *pci_find_present(const struct pci_device_id *ids)

{

{

	struct pci_dev *dev;

	struct pci_dev *dev;

	WARN_ON(in_interrupt());

	WARN_ON(in_interrupt());

	down_read(&pci_bus_sem);

	down_read(&pci_bus_sem);

 * find devices that are usually built into a system, or for a general hint as

 * find devices that are usually built into a system, or for a general hint as

 * to if another device happens to be present at this specific moment in time.

 * to if another device happens to be present at this specific moment in time.

 */

 */

int pci_dev_present(const struct pci_device_id *ids)

int pci_dev_present(const struct pci_device_id *ids)

{

{

	return pci_find_present(ids) == NULL ? 0 : 1;

	return pci_find_present(ids) == NULL ? 0 : 1;

		VMLINUX_SYMBOL(__start_pci_fixups_enable) = .;		\

		VMLINUX_SYMBOL(__start_pci_fixups_enable) = .;		\

		*(.pci_fixup_enable)					\

		*(.pci_fixup_enable)					\

		VMLINUX_SYMBOL(__end_pci_fixups_enable) = .;		\

		VMLINUX_SYMBOL(__end_pci_fixups_enable) = .;		\

	}								\

	}								\

									\

									\

	/* RapidIO route ops */						\

	/* RapidIO route ops */						\

 */

 */

#define pci_module_init	pci_register_driver

#define pci_module_init	pci_register_driver

/* these external functions are only available when PCI support is enabled */

/* these external functions are only available when PCI support is enabled */

#ifdef CONFIG_PCI

#ifdef CONFIG_PCI

	pci_fixup_header,	/* After reading configuration header */

	pci_fixup_header,	/* After reading configuration header */

	pci_fixup_final,	/* Final phase of device fixups */

	pci_fixup_final,	/* Final phase of device fixups */

	pci_fixup_enable,	/* pci_enable_device() time */

	pci_fixup_enable,	/* pci_enable_device() time */

};

};

/* Anonymous variables would be nice... */

/* Anonymous variables would be nice... */

#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)			\

#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)			\

	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\

	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\

			vendor##device##hook, vendor, device, hook)

			vendor##device##hook, vendor, device, hook)

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);