Attachment 769879 Details for Bug 1092885

[patch] 0001-i386-Add-bit-2-of-SPEC_CTRL-MSR-support-SSBD.patch

0001-i386-Add-bit-2-of-SPEC_CTRL-MSR-support-SSBD.patch (text/plain), 1.84 KB, created by Marcus Meissner on 2018-05-11 09:11:47 UTC

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Creator: Marcus Meissner

Created: 2018-05-11 09:11:47 UTC

Size: 1.84 KB

patch

obsolete

>From 00dbdaa9813ec9fbeb035d96a088a429b1231a93 Mon Sep 17 00:00:00 2001
>From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
>Date: Wed, 11 Apr 2018 17:26:51 -0400
>Subject: [PATCH v3] i386: Add bit(2) of SPEC_CTRL MSR support - SSBD
>
>i386: Add bit(2) of SPEC_CTRL MSR support - Reduced Data Speculation
>
>Now users can do:
>
>cpu host,+spec-ctrl,+ssbd
>
>to have both IBRS and SSBD support.
>
>Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
>---
>
>v3: s/ssb/rds/
>v4: s/spec_store_bypass/rds/
>    s/MDD/Reduced Data Speculation/
>v5: Rip it out of the builtin_x86_defs per Paolo's recommendation
>    s/RDS/SSBD/
>
> target/i386/cpu.c | 22 +++++++++++-----------
> target/i386/cpu.h |  1 +
> 2 files changed, 12 insertions(+), 11 deletions(-)
>
>diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>index 39e791f..6256e48 100644
>--- a/target/i386/cpu.c
>+++ b/target/i386/cpu.c
>@@ -459,7 +459,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WOSSBD] = {
>             NULL, NULL, NULL, NULL,
>             NULL, NULL, NULL, NULL,
>             NULL, NULL, "spec-ctrl", NULL,
>-            NULL, NULL, NULL, NULL,
>+            NULL, NULL, NULL, "ssbd",
>         },
>         .cpuid_eax = 7,
>         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
>diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>index 2d71bc9..ff604cd 100644
>--- a/target/i386/cpu.h
>+++ b/target/i386/cpu.h
>@@ -650,6 +650,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WOSSBD];
> #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
> #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
>+#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
> 
> #define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */
> 
>-- 
>1.8.3.1
>

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Attachments on bug 1092885: 769875 | 769879 | 770168