Attachment 827151 Details for Bug 1160204

Output of cpuid as requested by Thomas Renninger

cpuid (text/plain), 1.67 MB, created by Will Bainbridge on 2020-01-08 12:47:26 UTC

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Creator: Will Bainbridge

Created: 2020-01-08 12:47:26 UTC

Size: 1.67 MB

patch

obsolete

>CPU 0:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x0 (0)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 0
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 0
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 0
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x0 (0)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
>   (synth) = unknown
>CPU 1:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x2 (2)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 2
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 2
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 2
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x1 (1)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
>   (synth) = unknown
>CPU 2:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x4 (4)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 4
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 4
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 4
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x2 (2)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
>   (synth) = unknown
>CPU 3:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x6 (6)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 6
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 6
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 6
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x3 (3)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=6 SMT_ID=0
>   (synth) = unknown
>CPU 4:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8 (8)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 8
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 8
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 8
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x4 (4)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
>   (synth) = unknown
>CPU 5:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xa (10)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 10
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 10
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 10
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x5 (5)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
>   (synth) = unknown
>CPU 6:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xc (12)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 12
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 12
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 12
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x6 (6)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
>   (synth) = unknown
>CPU 7:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xe (14)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 14
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 14
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 14
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x7 (7)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=14 SMT_ID=0
>   (synth) = unknown
>CPU 8:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x10 (16)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 16
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 16
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 16
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x8 (8)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=16 SMT_ID=0
>   (synth) = unknown
>CPU 9:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x12 (18)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 18
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 18
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 18
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x9 (9)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=18 SMT_ID=0
>   (synth) = unknown
>CPU 10:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x14 (20)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 20
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 20
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 20
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xa (10)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=20 SMT_ID=0
>   (synth) = unknown
>CPU 11:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x16 (22)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 22
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 22
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 22
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xb (11)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=22 SMT_ID=0
>   (synth) = unknown
>CPU 12:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x18 (24)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 24
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 24
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 24
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xc (12)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=24 SMT_ID=0
>   (synth) = unknown
>CPU 13:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1a (26)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 26
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 26
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 26
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xd (13)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=26 SMT_ID=0
>   (synth) = unknown
>CPU 14:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1c (28)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 28
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 28
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 28
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xe (14)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=28 SMT_ID=0
>   (synth) = unknown
>CPU 15:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1e (30)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 30
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 30
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 30
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xf (15)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=30 SMT_ID=0
>   (synth) = unknown
>CPU 16:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x80 (128)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 128
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 128
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 128
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x0 (0)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=0 SMT_ID=0
>   (synth) = unknown
>CPU 17:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x82 (130)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 130
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 130
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 130
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x1 (1)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=2 SMT_ID=0
>   (synth) = unknown
>CPU 18:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x84 (132)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 132
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 132
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 132
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x2 (2)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=4 SMT_ID=0
>   (synth) = unknown
>CPU 19:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x86 (134)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 134
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 134
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 134
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x3 (3)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=6 SMT_ID=0
>   (synth) = unknown
>CPU 20:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x88 (136)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 136
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 136
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 136
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x4 (4)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=8 SMT_ID=0
>   (synth) = unknown
>CPU 21:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8a (138)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 138
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 138
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 138
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x5 (5)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=10 SMT_ID=0
>   (synth) = unknown
>CPU 22:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8c (140)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 140
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 140
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 140
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x6 (6)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=12 SMT_ID=0
>   (synth) = unknown
>CPU 23:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8e (142)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 142
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 142
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 142
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x7 (7)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=14 SMT_ID=0
>   (synth) = unknown
>CPU 24:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x90 (144)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 144
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 144
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 144
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x8 (8)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=16 SMT_ID=0
>   (synth) = unknown
>CPU 25:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x92 (146)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 146
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 146
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 146
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x9 (9)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=18 SMT_ID=0
>   (synth) = unknown
>CPU 26:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x94 (148)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 148
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 148
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 148
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xa (10)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=20 SMT_ID=0
>   (synth) = unknown
>CPU 27:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x96 (150)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 150
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 150
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 150
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xb (11)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=22 SMT_ID=0
>   (synth) = unknown
>CPU 28:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x98 (152)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 152
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 152
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 152
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xc (12)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=24 SMT_ID=0
>   (synth) = unknown
>CPU 29:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9a (154)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 154
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 154
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 154
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xd (13)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=26 SMT_ID=0
>   (synth) = unknown
>CPU 30:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9c (156)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 156
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 156
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 156
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xe (14)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=28 SMT_ID=0
>   (synth) = unknown
>CPU 31:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9e (158)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 158
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 158
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 158
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xf (15)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=30 SMT_ID=0
>   (synth) = unknown
>CPU 32:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1 (1)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 1
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 1
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 1
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x0 (0)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
>   (synth) = unknown
>CPU 33:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x3 (3)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 3
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 3
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 3
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x1 (1)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
>   (synth) = unknown
>CPU 34:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x5 (5)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 5
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 5
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 5
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x2 (2)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
>   (synth) = unknown
>CPU 35:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x7 (7)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 7
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 7
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 7
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x3 (3)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=7 SMT_ID=0
>   (synth) = unknown
>CPU 36:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9 (9)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 9
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 9
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 9
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x4 (4)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
>   (synth) = unknown
>CPU 37:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xb (11)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 11
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 11
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 11
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x5 (5)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
>   (synth) = unknown
>CPU 38:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xd (13)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 13
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 13
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 13
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x6 (6)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
>   (synth) = unknown
>CPU 39:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0xf (15)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 15
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 15
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 15
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x7 (7)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=15 SMT_ID=0
>   (synth) = unknown
>CPU 40:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x11 (17)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 17
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 17
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 17
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x8 (8)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=17 SMT_ID=0
>   (synth) = unknown
>CPU 41:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x13 (19)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 19
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 19
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 19
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x9 (9)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=19 SMT_ID=0
>   (synth) = unknown
>CPU 42:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x15 (21)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 21
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 21
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 21
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xa (10)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=21 SMT_ID=0
>   (synth) = unknown
>CPU 43:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x17 (23)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 23
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 23
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 23
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xb (11)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=23 SMT_ID=0
>   (synth) = unknown
>CPU 44:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x19 (25)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 25
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 25
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 25
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xc (12)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=25 SMT_ID=0
>   (synth) = unknown
>CPU 45:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1b (27)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 27
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 27
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 27
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xd (13)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=27 SMT_ID=0
>   (synth) = unknown
>CPU 46:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1d (29)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 29
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 29
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 29
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xe (14)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=29 SMT_ID=0
>   (synth) = unknown
>CPU 47:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x1f (31)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 31
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 31
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 31
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xf (15)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x0 (0)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=0 CORE_ID=31 SMT_ID=0
>   (synth) = unknown
>CPU 48:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x81 (129)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 129
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 129
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 129
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x0 (0)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=1 SMT_ID=0
>   (synth) = unknown
>CPU 49:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x83 (131)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 131
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 131
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 131
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x1 (1)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=3 SMT_ID=0
>   (synth) = unknown
>CPU 50:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x85 (133)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 133
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 133
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 133
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x2 (2)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=5 SMT_ID=0
>   (synth) = unknown
>CPU 51:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x87 (135)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 135
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 135
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 135
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x3 (3)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=7 SMT_ID=0
>   (synth) = unknown
>CPU 52:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x89 (137)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 137
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 137
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 137
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x4 (4)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=9 SMT_ID=0
>   (synth) = unknown
>CPU 53:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8b (139)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 139
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 139
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 139
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x5 (5)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=11 SMT_ID=0
>   (synth) = unknown
>CPU 54:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8d (141)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 141
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 141
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 141
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x6 (6)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=13 SMT_ID=0
>   (synth) = unknown
>CPU 55:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x8f (143)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 143
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 143
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 143
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x7 (7)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=15 SMT_ID=0
>   (synth) = unknown
>CPU 56:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x91 (145)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 145
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 145
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 145
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x8 (8)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=17 SMT_ID=0
>   (synth) = unknown
>CPU 57:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x93 (147)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 147
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 147
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 147
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0x9 (9)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=19 SMT_ID=0
>   (synth) = unknown
>CPU 58:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x95 (149)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 149
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 149
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 149
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xa (10)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=21 SMT_ID=0
>   (synth) = unknown
>CPU 59:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x97 (151)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 151
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 151
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 151
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xb (11)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=23 SMT_ID=0
>   (synth) = unknown
>CPU 60:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x99 (153)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 153
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 153
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 153
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xc (12)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=25 SMT_ID=0
>   (synth) = unknown
>CPU 61:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9b (155)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 155
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 155
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 155
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xd (13)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=27 SMT_ID=0
>   (synth) = unknown
>CPU 62:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9d (157)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 157
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 157
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 157
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xe (14)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=29 SMT_ID=0
>   (synth) = unknown
>CPU 63:
>   vendor_id = "AuthenticAMD"
>   version information (1/eax):
>      processor type  = primary processor (0)
>      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
>      model           = 0x1 (1)
>      stepping id     = 0x0 (0)
>      extended family = 0x8 (8)
>      extended model  = 0x3 (3)
>      (simple synth)  = unknown
>   miscellaneous (1/ebx):
>      process local APIC physical ID = 0x9f (159)
>      cpu count                      = 0x20 (32)
>      CLFLUSH line size              = 0x8 (8)
>      brand index                    = 0x0 (0)
>   brand id = 0x00 (0): unknown
>   feature information (1/edx):
>      x87 FPU on chip                        = true
>      VME: virtual-8086 mode enhancement     = true
>      DE: debugging extensions               = true
>      PSE: page size extensions              = true
>      TSC: time stamp counter                = true
>      RDMSR and WRMSR support                = true
>      PAE: physical address extensions       = true
>      MCE: machine check exception           = true
>      CMPXCHG8B inst.                        = true
>      APIC on chip                           = true
>      SYSENTER and SYSEXIT                   = true
>      MTRR: memory type range registers      = true
>      PTE global bit                         = true
>      MCA: machine check architecture        = true
>      CMOV: conditional move/compare instr   = true
>      PAT: page attribute table              = true
>      PSE-36: page size extension            = true
>      PSN: processor serial number           = false
>      CLFLUSH instruction                    = true
>      DS: debug store                        = false
>      ACPI: thermal monitor and clock ctrl   = false
>      MMX Technology                         = true
>      FXSAVE/FXRSTOR                         = true
>      SSE extensions                         = true
>      SSE2 extensions                        = true
>      SS: self snoop                         = false
>      hyper-threading / multi-core supported = true
>      TM: therm. monitor                     = false
>      IA64                                   = false
>      PBE: pending break event               = false
>   feature information (1/ecx):
>      PNI/SSE3: Prescott New Instructions     = true
>      PCLMULDQ instruction                    = true
>      DTES64: 64-bit debug store              = false
>      MONITOR/MWAIT                           = true
>      CPL-qualified debug store               = false
>      VMX: virtual machine extensions         = false
>      SMX: safer mode extensions              = false
>      Enhanced Intel SpeedStep Technology     = false
>      TM2: thermal monitor 2                  = false
>      SSSE3 extensions                        = true
>      context ID: adaptive or shared L1 data  = false
>      SDBG: IA32_DEBUG_INTERFACE              = false
>      FMA instruction                         = true
>      CMPXCHG16B instruction                  = true
>      xTPR disable                            = false
>      PDCM: perfmon and debug                 = false
>      PCID: process context identifiers       = false
>      DCA: direct cache access                = false
>      SSE4.1 extensions                       = true
>      SSE4.2 extensions                       = true
>      x2APIC: extended xAPIC support          = false
>      MOVBE instruction                       = true
>      POPCNT instruction                      = true
>      time stamp counter deadline             = false
>      AES instruction                         = true
>      XSAVE/XSTOR states                      = true
>      OS-enabled XSAVE/XSTOR                  = true
>      AVX: advanced vector extensions         = true
>      F16C half-precision convert instruction = true
>      RDRAND instruction                      = true
>      hypervisor guest status                 = false
>   cache and TLB information (2):
>   processor serial number: 0083-0F10-0000-0000-0000-0000
>   MONITOR/MWAIT (5):
>      smallest monitor-line size (bytes)       = 0x40 (64)
>      largest monitor-line size (bytes)        = 0x40 (64)
>      enum of Monitor-MWAIT exts supported     = true
>      supports intrs as break-event for MWAIT  = true
>      number of C0 sub C-states using MWAIT    = 0x1 (1)
>      number of C1 sub C-states using MWAIT    = 0x1 (1)
>      number of C2 sub C-states using MWAIT    = 0x0 (0)
>      number of C3 sub C-states using MWAIT    = 0x0 (0)
>      number of C4 sub C-states using MWAIT    = 0x0 (0)
>      number of C5 sub C-states using MWAIT    = 0x0 (0)
>      number of C6 sub C-states using MWAIT    = 0x0 (0)
>      number of C7 sub C-states using MWAIT    = 0x0 (0)
>   Thermal and Power Management Features (6):
>      digital thermometer                     = false
>      Intel Turbo Boost Technology            = false
>      ARAT always running APIC timer          = true
>      PLN power limit notification            = false
>      ECMD extended clock modulation duty     = false
>      PTM package thermal management          = false
>      HWP base registers                      = false
>      HWP notification                        = false
>      HWP activity window                     = false
>      HWP energy performance preference       = false
>      HWP package level request               = false
>      HDC base registers                      = false
>      Intel Turbo Boost Max Technology 3.0    = false
>      HWP capabilities                        = false
>      HWP PECI override                       = false
>      flexible HWP                            = false
>      IA32_HWP_REQUEST MSR fast access mode   = false
>      ignoring idle logical processor HWP req = false
>      digital thermometer thresholds          = 0x0 (0)
>      hardware coordination feedback          = true
>      ACNT2 available                         = false
>      performance-energy bias capability      = false
>   extended feature flags (7):
>      FSGSBASE instructions                    = true
>      IA32_TSC_ADJUST MSR supported            = false
>      SGX: Software Guard Extensions supported = false
>      BMI1 instructions                        = true
>      HLE hardware lock elision                = false
>      AVX2: advanced vector extensions 2       = true
>      FDP_EXCPTN_ONLY                          = false
>      SMEP supervisor mode exec protection     = true
>      BMI2 instructions                        = true
>      enhanced REP MOVSB/STOSB                 = false
>      INVPCID instruction                      = false
>      RTM: restricted transactional memory     = false
>      RDT-M: Intel RDT monitoring              = true
>      deprecated FPU CS/DS                     = false
>      MPX: intel memory protection extensions  = false
>      RDT-A: Intel RDT allocation              = true
>      AVX512F: AVX-512 foundation instructions = false
>      AVX512DQ: double & quadword instructions = false
>      RDSEED instruction                       = true
>      ADX instructions                         = true
>      SMAP: supervisor mode access prevention  = true
>      AVX512IFMA: fused multiply add           = false
>      PCOMMIT instruction                      = false
>      CLFLUSHOPT instruction                   = true
>      CLWB instruction                         = true
>      Intel processor trace                    = false
>      AVX512PF: prefetch instructions          = false
>      AVX512ER: exponent & reciprocal instrs   = false
>      AVX512CD: conflict detection instrs      = false
>      SHA instructions                         = true
>      AVX512BW: byte & word instructions       = false
>      AVX512VL: vector length                  = false
>      PREFETCHWT1                              = false
>      AVX512VBMI: vector byte manipulation     = false
>      UMIP: user-mode instruction prevention   = true
>      PKU protection keys for user-mode        = false
>      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
>      WAITPKG instructions                     = false
>      AVX512_VBMI2                             = false
>      CET_SS: CET shadow stack                 = false
>      GFNI: Galois Field New Instructions      = false
>      VAES instructions                        = false
>      VPCLMULQDQ instruction                   = false
>      AVX512_VNNI                              = false
>      AVX512_BITALG: bit count/shiffle         = false
>      AVX512: VPOPCNTDQ instruction            = false
>      5-level paging                           = false
>      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
>      RDPID: read processor D supported        = true
>      CLDEMOTE supports cache line demote      = false
>      MOVDIRI instruction                      = false
>      MOVDIR64B intruction                     = false
>      SGX_LC: SGX launch config supported      = false
>      AVX512_4VNNIW: neural network instrs     = false
>      AVX512_4FMAPS: multiply acc single prec  = false
>      fast short REP MOV                       = false
>      PCONFIG                                  = false
>      CET_IBT: CET indirect branch tracking    = false
>   Direct Cache Access Parameters (9):
>      PLATFORM_DCA_CAP MSR bits = 0
>   Architecture Performance Monitoring Features (0xa/eax):
>      version ID                               = 0x0 (0)
>      number of counters per logical processor = 0x0 (0)
>      bit width of counter                     = 0x0 (0)
>      length of EBX bit vector                 = 0x0 (0)
>   Architecture Performance Monitoring Features (0xa/ebx):
>      core cycle event not available           = false
>      instruction retired event not available  = false
>      reference cycles event not available     = false
>      last-level cache ref event not available = false
>      last-level cache miss event not avail    = false
>      branch inst retired event not available  = false
>      branch mispred retired event not avail   = false
>   Architecture Performance Monitoring Features (0xa/edx):
>      number of fixed counters    = 0x0 (0)
>      bit width of fixed counters = 0x0 (0)
>      anythread deprecation       = false
>   x2APIC features / processor topology (0xb):
>      --- level 0 (thread) ---
>      bits to shift APIC ID to get next = 0x1 (1)
>      logical processors at this level  = 0x2 (2)
>      level number                      = 0x0 (0)
>      level type                        = thread (1)
>      extended APIC ID                  = 159
>      --- level 1 (core) ---
>      bits to shift APIC ID to get next = 0x7 (7)
>      logical processors at this level  = 0x20 (32)
>      level number                      = 0x1 (1)
>      level type                        = core (2)
>      extended APIC ID                  = 159
>   XSAVE features (0xd/0):
>      XCR0 lower 32 bits valid bit field mask = 0x00000207
>      XCR0 upper 32 bits valid bit field mask = 0x00000000
>         XCR0 supported: x87 state            = true
>         XCR0 supported: SSE state            = true
>         XCR0 supported: AVX state            = true
>         XCR0 supported: MPX BNDREGS          = false
>         XCR0 supported: MPX BNDCSR           = false
>         XCR0 supported: AVX-512 opmask       = false
>         XCR0 supported: AVX-512 ZMM_Hi256    = false
>         XCR0 supported: AVX-512 Hi16_ZMM     = false
>         IA32_XSS supported: PT state         = false
>         XCR0 supported: PKRU state           = true
>         IA32_XSS supported: HDC state        = false
>      bytes required by fields in XCR0        = 0x00000340 (832)
>      bytes required by XSAVE/XRSTOR area     = 0x00000380 (896)
>   XSAVE features (0xd/1):
>      XSAVEOPT instruction                        = true
>      XSAVEC instruction                          = true
>      XGETBV instruction                          = true
>      XSAVES/XRSTORS instructions                 = true
>      SAVE area size in bytes                     = 0x00000340 (832)
>      IA32_XSS lower 32 bits valid bit field mask = 0x00000000
>      IA32_XSS upper 32 bits valid bit field mask = 0x00000000
>   AVX/YMM features (0xd/2):
>      AVX/YMM save state byte size             = 0x00000100 (256)
>      AVX/YMM save state byte offset           = 0x00000240 (576)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   PKRU features (0xd/9):
>      PKRU save state byte size                = 0x00000040 (64)
>      PKRU save state byte offset              = 0x00000340 (832)
>      supported in IA32_XSS or XCR0            = XCR0 (user state)
>      64-byte alignment in compacted XSAVE     = false
>   Quality of Service Monitoring Resource Type (0xf/0):
>      Maximum range of RMID = 255
>      supports L3 cache QoS monitoring = false
>   L3 Cache Quality of Service Monitoring (0xf/1):
>      Conversion factor from IA32_QM_CTR to bytes = 64
>      Maximum range of RMID                       = 255
>      supports L3 occupancy monitoring       = true
>      supports L3 total bandwidth monitoring = true
>      supports L3 local bandwidth monitoring = true
>   Resource Director Technology allocation (0x10/0):
>      L3 cache allocation technology supported = true
>      L2 cache allocation technology supported = false
>      memory bandwidth allocation supported    = false
>   L3 Cache Allocation Technology (0x10/1):
>      length of capacity bit mask - 1 = 0xf (15)
>      Bit-granular map of isolation/contention    = 0x00000000
>      infrequent updates of COS              = false
>      code and data prioritization supported = true
>      highest COS number supported = 0xf (15)
>   extended processor signature (0x80000001/eax):
>      family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
>      model             = 0x1 (1)
>      stepping id       = 0x0 (0)
>      extended family   = 0x8 (8)
>      extended model    = 0x3 (3)
>      (simple synth) = unknown
>   extended feature flags (0x80000001/edx):
>      x87 FPU on chip                       = true
>      virtual-8086 mode enhancement         = true
>      debugging extensions                  = true
>      page size extensions                  = true
>      time stamp counter                    = true
>      RDMSR and WRMSR support               = true
>      physical address extensions           = true
>      machine check exception               = true
>      CMPXCHG8B inst.                       = true
>      APIC on chip                          = true
>      SYSCALL and SYSRET instructions       = true
>      memory type range registers           = true
>      global paging extension               = true
>      machine check architecture            = true
>      conditional move/compare instruction  = true
>      page attribute table                  = true
>      page size extension                   = true
>      multiprocessing capable               = false
>      no-execute page protection            = true
>      AMD multimedia instruction extensions = true
>      MMX Technology                        = true
>      FXSAVE/FXRSTOR                        = true
>      SSE extensions                        = true
>      1-GB large page support               = true
>      RDTSCP                                = true
>      long mode (AA-64)                     = true
>      3DNow! instruction extensions         = false
>      3DNow! instructions                   = false
>   extended brand id (0x80000001/ebx):
>      raw     = 0x40000000 (1073741824)
>      BrandId = 0x0 (0)
>   AMD feature flags (0x80000001/ecx):
>      LAHF/SAHF supported in 64-bit mode     = true
>      CMP Legacy                             = true
>      SVM: secure virtual machine            = true
>      extended APIC space                    = true
>      AltMovCr8                              = true
>      LZCNT advanced bit manipulation        = true
>      SSE4A support                          = true
>      misaligned SSE mode                    = true
>      3DNow! PREFETCH/PREFETCHW instructions = true
>      OS visible workaround                  = true
>      instruction based sampling             = true
>      XOP support                            = false
>      SKINIT/STGI support                    = true
>      watchdog timer support                 = true
>      lightweight profiling support          = false
>      4-operand FMA instruction              = false
>      TCE: translation cache extension       = true
>      NodeId MSR C001100C                    = false
>      TBM support                            = false
>      topology extensions                    = true
>      core performance counter extensions    = true
>      data breakpoint extension              = true
>      performance time-stamp counter support = false
>      performance counter extensions         = true
>      MWAITX/MONITORX supported              = true
>   brand = "AMD EPYC 7282 16-Core Processor                "
>   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = 0xff (255)
>      data # entries            = 0x40 (64)
>      data associativity        = 0xff (255)
>   L1 data cache information (0x80000005/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L1 instruction cache information (0x80000005/edx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 0x8 (8)
>      size (KB)         = 0x20 (32)
>   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 4-way (4)
>   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
>      instruction # entries     = 0x400 (1024)
>      instruction associativity = 8-way (6)
>      data # entries            = 0x800 (2048)
>      data associativity        = 8-way (6)
>   L2 unified cache information (0x80000006/ecx):
>      line size (bytes) = 0x40 (64)
>      lines per tag     = 0x1 (1)
>      associativity     = 8-way (6)
>      size (KB)         = 0x200 (512)
>   L3 cache information (0x80000006/edx):
>      line size (bytes)     = 0x40 (64)
>      lines per tag         = 0x1 (1)
>      associativity         = 0x9 (9)
>      size (in 512KB units) = 0x80 (128)
>   RAS Capability (0x80000007/ebx):
>      MCA overflow recovery support = true
>      SUCCOR support                = true
>      HWA: hardware assert support  = false
>      scalable MCA support          = true
>   Advanced Power Management Features (0x80000007/ecx):
>      CmpUnitPwrSampleTimeRatio = 0x0 (0)
>   Advanced Power Management Features (0x80000007/edx):
>      TS: temperature sensing diode           = true
>      FID: frequency ID control               = false
>      VID: voltage ID control                 = false
>      TTP: thermal trip                       = true
>      TM: thermal monitor                     = true
>      STC: software thermal control           = false
>      100 MHz multiplier control              = false
>      hardware P-State control                = true
>      TscInvariant                            = true
>      CPB: core performance boost             = true
>      read-only effective frequency interface = true
>      processor feedback interface            = false
>      APM power reporting                     = false
>      connected standby                       = true
>      RAPL: running average power limit       = true
>   Physical Address and Linear Address Size (0x80000008/eax):
>      maximum physical address bits         = 0x30 (48)
>      maximum linear (virtual) address bits = 0x30 (48)
>      maximum guest physical address bits   = 0x0 (0)
>   Extended Feature Extensions ID (0x80000008/ebx):
>      CLZERO instruction                 = true
>      instructions retired count support = true
>      always save/restore error pointers = true
>   Logical CPU cores (0x80000008/ecx):
>      number of CPU cores - 1 = 0x1f (31)
>      ApicIdCoreIdSize        = 0x7 (7)
>   SVM Secure Virtual Machine (0x8000000a/eax):
>      SvmRev: SVM revision = 0x1 (1)
>   SVM Secure Virtual Machine (0x8000000a/edx):
>      nested paging                          = true
>      LBR virtualization                     = true
>      SVM lock                               = true
>      NRIP save                              = true
>      MSR based TSC rate control             = true
>      VMCB clean bits support                = true
>      flush by ASID                          = true
>      decode assists                         = true
>      SSSE3/SSE5 opcode set disable          = false
>      pause intercept filter                 = true
>      pause filter threshold                 = true
>      AVIC: AMD virtual interrupt controller = true
>      virtualized VMLOAD/VMSAVE              = true
>      virtualized GIF                        = true
>   NASID: number of address space identifiers = 0x8000 (32768):
>   L1 TLB information: 1G pages (0x80000019/eax):
>      instruction # entries     = 0x40 (64)
>      instruction associativity = full (15)
>      data # entries            = 0x40 (64)
>      data associativity        = full (15)
>   L2 TLB information: 1G pages (0x80000019/ebx):
>      instruction # entries     = 0x0 (0)
>      instruction associativity = L2 off (0)
>      data # entries            = 0x0 (0)
>      data associativity        = L2 off (0)
>   SVM Secure Virtual Machine (0x8000001a/eax):
>      128-bit SSE executed full-width = false
>      MOVU* better than MOVL*/MOVH*   = true
>      256-bit SSE executed full-width = true
>   Instruction Based Sampling Identifiers (0x8000001b/eax):
>      IBS feature flags valid                  = true
>      IBS fetch sampling                       = true
>      IBS execution sampling                   = true
>      read write of op counter                 = true
>      op counting mode                         = true
>      branch target address reporting          = true
>      IbsOpCurCnt and IbsOpMaxCnt extend 7     = true
>      invalid RIP indication support           = true
>      fused branch micro-op indication support = true
>      IBS fetch control extended MSR support   = true
>      IBS op data 4 MSR support                = false
>   Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
>      lightweight profiling                  = false
>      LWPVAL instruction                     = false
>      instruction retired event              = false
>      branch retired event                   = false
>      DC miss event                          = false
>      core clocks not halted event           = false
>      core reference clocks not halted event = false
>      interrupt on threshold overflow        = false
>   Lightweight Profiling Capabilities (0x8000001c/ebx):
>      LWPCB byte size             = 0x0 (0)
>      event record byte size      = 0x0 (0)
>      maximum EventId             = 0x0 (0)
>      EventInterval1 field offset = 0x0 (0)
>   Lightweight Profiling Capabilities (0x8000001c/ecx):
>      latency counter bit size          = 0x0 (0)
>      data cache miss address valid     = false
>      amount cache latency is rounded   = 0x0 (0)
>      LWP implementation version        = 0x0 (0)
>      event ring buffer size in records = 0x0 (0)
>      branch prediction filtering       = false
>      IP filtering                      = false
>      cache level filtering             = false
>      cache latency filteing            = false
>   Cache Properties (0x8000001d):
>      --- cache 0 ---
>      type                            = data (1)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 1 ---
>      type                            = instruction (2)
>      level                           = 0x1 (1)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 63
>      write-back invalidate           = false
>      cache inclusive of lower levels = false
>      --- cache 2 ---
>      type                            = unified (3)
>      level                           = 0x2 (2)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x1 (1)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0x7 (7)
>      number of sets                  = 1023
>      write-back invalidate           = false
>      cache inclusive of lower levels = true
>      --- cache 3 ---
>      type                            = unified (3)
>      level                           = 0x3 (3)
>      self-initializing               = true
>      fully associative               = false
>      extra cores sharing this cache  = 0x7 (7)
>      line size in bytes              = 0x3f (63)
>      physical line partitions        = 0x0 (0)
>      number of ways                  = 0xf (15)
>      number of sets                  = 16383
>      write-back invalidate           = true
>      cache inclusive of lower levels = false
>   extended APIC ID = 159
>   Extended APIC ID (0x8000001e/ebx):
>      compute unit ID            = 0xf (15)
>      cores per compute unit - 1 = 0x1 (1)
>   Extended APIC ID (0x8000001e/ecx):
>      node ID             = 0x1 (1)
>      nodes per processor = 1 node (0)
>   SME/SEV (0x8000001f):
>      SME: secure memory encryption support    = true
>      SEV: secure encrypted virtualize support = true
>      MIN_SEV_ASID = 0x1 (1)
>      MAX_SEV_ASID = 0x1fd (509)
>   0x80000020 0x00: eax=0x00000000 ebx=0x00000002 ecx=0x00000000 edx=0x00000000
>   (instruction supported synth):
>      CMPXCHG8B                = true
>      conditional move/compare = true
>      PREFETCH/PREFETCHW       = true
>   (multi-processing synth): multi-core (c=32)
>   (multi-processing method): AMD
>   (APIC widths synth): CORE_width=5 SMT_width=0
>   (APIC synth): PKG_ID=4 CORE_ID=31 SMT_ID=0
>   (synth) = unknown

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Attachments on bug 1160204: 827150 | 827151